Magnetic core driver and system



Nov. 14, 1967 E. c. BOWLING MAGNETIC CORE DRIVER AND SYSTEM Filed Aug. 16, 1963 2 Sheets-Sheet 1 INVENTOR. aa/Mza t aw va QMV ATTA/E/f mmm UN 2 Sheets-Sheet 2 C. 6 r/u. L @w 4 L F Tzl mw; y l ||l f IW W r A, f P W Q 11X fx NOV- 14, 1957 E. C. BOWLING MAGNETIC CURE DRIVER AND SYSTEM Filed Aug. 16, 1963 @aan SETI bil/77H72:-

SHIPLEI SMPI g SETE? United States Patent O Filed Aug. 16, 1963, Ser. No. 302,497 2 Claims. (Cl. 340-174) ABSTRACT F THE DISCLOSURE A series of magnetic control cores are connected together to be sequentially energized to in turn sequentially sample a plurality of magnetic core stages, one stage for each control core. Interposed in circuit -between each control core is a sampling driver powered by a separate power supply but triggered by the clearing of an associated control core to effect stage sampling and to set a succeeding control core.

Background of the invention The magnetic core device has a basic comparative advantage over other solid state devices with respect to inherent simplicity of function and over-all reliability. When used in the more complex intelligence handling systems, however, the prior art has tended to offset this advantage through the use of peripheral support equipment which is complex from a standpoint of duplication of parts and operation. This is particularly true in systems wherein a large number of distinct magnetic core units such as shift registers must be sampled in some ordered sequence to provide a given system function. One of the specific problems relative to such applications has been with regard to the cycle control for systems and the necessary use of additional trigger sources for each driver associated with each stage of the magnetic core units as `well as the incident requirement 0f specialized synchronization for such sources.

Summary of the invention This invention relates to the system and means for sampling the intelligence content of magnetic core devices in the sequenced and automatic fashion.

Accordingly, it is one object of the invention to provide a simple and inexpensive cycle control system for sequentially operating numbers of distinct magnetic unit stages within a system.

It is a further object of invention to provide an improved cycle control circuit in conjunction with a magnetic core driver capable of providing both magnetic core drive pulses and necessary trigger pulses automatically.

It is another object of the invention to provide a novel driver capable of use in sampling magnetic cores with an automatic delay before providing -a trigger to the next stage of the system.

Other objects and attainments of the present invention will become apparent to those skilled in the art upon a reading of the following detailed description when taken in conjunction with the drawings in which there -are shown :and described illustrative embodiments of the invention; it is to be understood, however, that these embodiments are not intended to be exhaustive nor limiting of the invention, but are given for purposes of illustration in order that others skilled in the art may fully understand the invention and the principles thereof and the manner of applying it in practical use so that they may modify it in various forms, each as may be best suited t-o the conditions of a particular use.

In the drawings: i

FlGURE l is a schematic diagram representing a porlCe tion of a system for manipulating intelligence in binary form in conj-unction with the novel cycle control circuit of the invention;

FIGURE 2 is a time sequence diagram depicting the operation of the cycle control circuit of FIGURE l;

FIGURE 3 is a schematic diagram of the novel driver of the invention; and

FIGURE 4 is a diagram of current and voltage values versus time developed by the circuit of FIGURE 3.

Description of preferred embodiment Turning now to FIGURE 1, iblock 10 may be taken to represent a system for performing some intelligence manipulation function wherein 'a series of distinct stages of the system must be sequentially sampled for intelligence content. Systems of this type are used in almost every 'area of communications, telemetering, computing and the like. In the example shown, block 10 may be taken to include a series of stages I, II, III, N, each comprised of an array of magnetic cores arranged to provide multiple outputs in an ordered fashion. Such outputs may `be indicative of digital codes fed into and/ or shifted between the cores in a manner not shown. Alternatively, the outputs provided from each stage may represent a particular decimal count of some quantity, as for example a count of time increments with the position of the output associated with a given decimal value. In such systems it is frequently necessary that the outputs from a given stage I-N be sampled sequentially for equipment sharing purposes. For example, each of the outputs I-N might necessarily be supplied to some other portion of the system on a time-division multiplex basis so that a single sensing mechanism 'and perhaps a single recording mechanism could be utilized to receive, record and utilize the inputs from each stage. Thus, the system requirement would call for a readout of stage I, followed by a readout of stage II, followed fby a readout of stage III -and so forth.

The exemplary readout shown with respect to stage I is a so-called non-destructive readout `from multi-aperture magnetic cores. The technique of this is generally understood in the art, which frequently refers to such readout as a static output. Brieiiy summarized, the representative stage I-N include uniti, 12, 14, 16 and 18, which may be identical in structure including a number of multi-aperture magnetic cores such as the two cores 14 and 16 shown in unit 12. The particular means for setting intelligence into or shifting intelligence between cores 14 and 16 is not shown, but may be by any of the standard core transfer techniques. The sampling mechanism may be followed by rst considering core 14 to be set or in the one state (half positive, half negative saturation) and core 16 to be cleared or in the zero state (full negative saturation) to define an intelligence content of one and zero for the two cores, respectively. A pulse of sutiicient amplitude applied on a sampling winding threading a minor aperture of each core will operate t0 switch remanent flux under an output loop if the core is set, but not switch remanent flux if the core is clear due to the existence or non-existence of a possible path of flux closure around the minor aperture 15 in conjunction with a lower set threshold. Thus, under the above conditions a pulse applied to sampling winding 18 will cause remanent flux to be switched around aperture 15 of core 14, but not around aperture 17 of core 16. The fiux switched in core 14 will induce a voltage proportional to the rate of flux switched and thereby an output on winding 20 threading the outer leg of core 14 through aperture 15. Output winding 22 will see no flux switched and accordingly produce no output voltage. This effectively samples the intelligence states of the cores 14 and 16 by producing a one level pulse on output winding 20 indicating that core 14 contains a one (is set) and by producing a zero level output pulse on winding 22 indicating that core 16 is clear. By regulating the amplitude and duration of the sampling pulse to values below the major aperture set threshold, the core may be non-destructively sampled. As will be readily appreciated, the position of a single one physically in the unit 12 may indicate the decimal count of such unit in counter applications. Alternatively, a given pattern or code of ones or zeros in unit 12 may convey other intelligence significance.

In accordance with system requirements, after stage I has been sampled and its output provided it is necessary to then sample stage II, which may bey considered to be composed of cores and a sampling-output circuit identical to that of stage I. The succeeding stages III will thereafter be s ampled in sequence. The completed sequence of sampling of stages I-N may be considered as a system cycle. It is fully contemplated that each of the stages may be different to perform a different function; the combined functions operating to complete a system function. The readout for each would, of course, be the same.

The present invention relates to a cycle control for the system shown in block 10, including a means for initiating the cycle and means for automatically assuring the proper sequence of sampling for each of the stages. The most important aspect of the invention is its relative simplicity and the improved reliability which goes therewith. Viewing FIGURE 1 again, block 30 represents the cycle control circuit of the invention. Feeding this circuit is a lead 32 supplied by the basic clock of the over-all system which may be considered as comprised of a number of pulses each associated with a given sequence of operation. The clock, as shown in FIGURE 2, is comprised of equally spaced pulses of the same amplitude and duration and may be considered as generated by any standard pulse forming device. Included in the cycle control 30 are a number of magnetic cores 1, 2 3 and n with one core associated with each stage I, II, III n of system 10. Each of the cores 1-n are shown as multi-aperture cores and may be considered as. identical to the cores 14 and 16 in the device 10, which feature permits the same cores to be utilized throughout the system thus reducing the number of different parts needed and assuring that the characteristics of the cycle control cores will be identical to those of the cores in the associated circuit. It is contemplated that other types of magnetic cores may be utilized in lieu of the cores l-n shown. In such event, however, the differences in operating characteristics with respect to temperature, signal frequency, required number of turns and pulse shapes must be taken into consideration.

The basic clock source is supplied in series to each of the cores 1-11 by having the winding 32 link each core through a major aperture in a sense such that the clock pulse current IC clears each core simultaneously by turns Nc as shown. As compared with prior art techniques wherein the initiation of a given stage of a system is accomplished through separate clock circuits, the cycle control 30 of the invention may be seen to be a substantial improvement, since the same physical winding is utilized for each stage to thereby eliminate the need for synchronization between cycle control stages as well as necessary electrical isolation therebetween.

Linking the first stage of the cycle control 30 is an initiating circuit 34 including a winding 36 linking core 1 by turns N,- in a sense to set the core responsive to the application of a current IS on lead 36. The initiatin-g device 34 includes a switch 38, which upon closure connects lead 36 to the positive side of battery 40 to complete a circuit through Nr to ground, A schematic representation of the initiating device 34 is intended to represent not only an electro-mechanical-nranual type of initiation, but also electronic types wherein the switch 38 would be replaced with a solid state device such as-a transistor triggered to briefly conduct responsive to a control pulse` applied from some remotely controlled external source, elther manually or automatically. Further linking core `1 is an output trigger lwinding 42 rhaving turns NL linking the major aperture thereof so that when core 1 is cleared from a set condition an output pulse IT will be produced flowing in lead 42 to the associated sampling driver 50. This pulse serves to trigger 50 and provide an operation to lbe hereinafter described lwhich will produce an output pulse from 50 via leads 52 of the stage I of the system 10 and also, after a delay, an output pulse on lead 54 to the next cycle control unit through turns N1r linking core 2 in a sense to set such core. The operation of the cycle control in stages II, III and N with respect to the respective sampling drivers associated therewith is the same as that of stage I, except that the initiating device for core 1 is replaced by a `lead from the preceding sampling driver, as for example, lead 54 from sampling driver 50.

The operation of the circuit of FIGURE 1 may be better appreciated by viewing the time sequence diagram shown in FIGURE 2. The upper curve represents the clock supplied by lead 32 which, as heretofore mentioned, is the basic system clock with each of the pulses shown spaced so as to define a proper timing for the sampling operation of t-he stages I-N of system 10, and frequently supplied to other leads for the operation of other system equipment. Although the clock pulses shown in FIGa URE 2 are equally spaced, in certain instances it may be desirable to have different time spacings to provide different delays between sampling operations of the difierent stages. Considering the left hand pulse to be the first pulse in time, the following closure of switch 38 will produce a pulse shown as the Set I initiate pulse in FIG- URE 2, lwhich `will operate to set core 1. The tiux..

switched as core 1 is set, will, of course, induce a voltage. in `turns Nt, but as hereinafterwill be shown, such will be of a polarity not suitable to trigger sampling driver 50. T he cycling control circuit 30 at this point is initiated, butwill not respond to produce a trigger to 50 to sample stage I of system 10 until the next occurring clock pulseA In FIGURE 2 then, following the first pulse of the clock `we see the circuits 30 and 10 as being at rest with core number 1 set. The second clock pulse operates to apply a clearing MMF Nc IC to each of the cores 1-n which switches core 1 from the set state to the clear state and merely' drives the remaining cores further into negative saturation. As core 1 is switched lead 42 will experience a voltage `of a polari-ty proper to operate sampling driver 50. This is shown in FIGURE 2 as the Sample I pulse. The remaining sampling drivers associated with cores 2-n are, of course, not operated at this time. As the Sample I pulse curve shown in FIGURE 4 indicates, there is a gradually rising positive portion P immediately followed by a relatively large negative portion A. With respect to the operation of 30, the positive portion merely represents a delay and the negative portion is utilized via winding S4 to set core 2.1Both the positive and negative portions are supplied to -unit 12 of stage I to effect stage I sampling. This is shown in FIGURE 2 as I Output wherein a pattern of pulses representing the particular intelligence state of stage I is shown in serial form. It will be appreciated that the arrangement shown for 12 produces a parallel output and the output representations in FIGURE 2 are merely to show the timing and indie cate different intelligence contents for the stages I-N.

The delay provided by the positive portion P of the Sample I pulse permits the use` of a commoned cycle control clock drive. Otherwise the setting pulse would be applied to the next core while such core was under the clearing MMF of the clock and there would be no transfer to the next core and there could be no sequenced operation. For this reason, the prior art approach utilizes separate circuits for each of the cycle control stages. The Set II pulse operating to set cycle control core 2 works in the same manner as the SetI Initiate pulse and sampling of stage II is, of course, dependent upon the next occurring clock pulse which produces the Sample II pulse shown in FIGUR- After the delay shown by'the positive portion of such pulse, a Set II pulse is developed setting the core 3 of the cycle control. The next occurring clock pulse continues the process with the succeeding cores of the cycle control through N being operated to produce their respective outputs and cause the stages to be sampled.

With the foregoing in mind several variations of the circuit of FIGURE 1 may be readily developed if system requirements so demand. First, the particular sequence of sampling may be changed by merely changing the y-y' terminal leads to drive a different sampling core and the trigger winding of such core to link a different sampling driver. For example, lead 54 could be made to drive core n with the sampling driver for n connected to set core 2, which in turn would have its sampling driver linked to core 3. This would effect a sampling sequence of stages I, N, II and III. In a similar fashion any sequence could be obtained from the same basic clock with only changes internal to 30 being necessitated. If desired, the capability to change the cycle control sequence can be facilitated by a suitable tap changing device such as a pinboard or plugboard to program the core coupling in distinct patterns. Secondly, the cycle control can be lutilized to develop trains of fixed pulses or codes. In such use the unit 30 would be as shown and the system would be wired essentially as shown with the addition of a single winding threading each of the cores of stages I-N in a pattern to set only certain of the cores of each stage and clear all Vothers to develop code trains to be generated. With this and the initiation -of 34, the clock would function as above described to sequentially produce distinct codes from each stage.

In conjunction with the cycle control circuit above described, the invention contemplates a specialized sampling driver which provides the necessary functions for the device of FIGURE l with a minimum of components.

In FIGURE 3 it will be -observed that the appropriate terminals x-x and y-y', as well as the trigger input, are as identified in the sampling driver 50 shown in FIG- URE 1. The sampling driver of FIGURE 3, of course, has a direct utility with the circuit of FIGURE 1, but includes a broader utility for use in supplying advance and priming pulses for other MAD-R (multi-aperture device-resistance) units. The technique employed in the sampling driver shown in FIGURE 3 is in certain respects similar to that of an earlier filed application, Serial No. 52,295, now Patent No. 3,221,176, filed August 26, 1960, in the names of W. B. Fritz and I. H. Whitley as well as in U.S. application 114,695, now Patent No. 3,154,693, filed June 5, 1961, in the name of L. G. Wiley. Basically, the driver of FIGURE 3, as Well as the drivers of the above mentioned applications, are designed to provide pulses of characteristics tailored to meet the needs of magnetic core circuits wherein relatively low amplitude pulses of substantial length are needed for the priming function and relatively high amplitude short pulses are required for the advance function.

Viewing now the components of the driver of FIG- URE 3, a supply VS, which may be a battery source of; for example 40 volts, is shown as 60. Connected to source 60 is a capacitor (C1) shunted by a resistor 64 in series with an inductor 66 (L1) all forming part of a series resonant charging circuit. A rst switch 68 is supplied by Vs and has a threshold or switching voltage greater than the supply Vs as, for example, 50 volts. A typical device utilized for switch 68 is a four-layer diode Shockley No. 4E50. Provided on the output side of 68 is a trigger input 70, including in series a resistor 72 adapted to reduce the load as core 1 (of 30 in FIGURE l) is set. In the general case trigger lead 70 may be considered as supplied by a negative pulse of an amplitude sufficient when combined with VS to place a potential across 68 suliicient to lire the switch; eg. a voltage greater than 10 volts. Referring back to FIGURE l, trigger lead 70 may be taken as Vconnected to the output Winding 42 from core 1. Also connected to the output of 68 is a further lead including a diode 74 in series with a rst path including a further switch 76, which may be a fourlayer diode having a switching voltage something less than that of 68, as for example, 30 volts. In an actual circuit utilized, 76 was a Shockley No. 4E30. In series with switch 76 and constituting a further branch of the series resonant circuit is a capacitor 78 (C2), an inductor 80 (L2) and a resistor 82 connected to ground. In an actual circuit 78 had a value of .15 microfarad. As indicated in FIGURE 3, the three legs depicted as w-w,

v shown in FIGURE 4, which depicts against time in microseconds as viewed from top to bottom, current, voltage and current, respectively.

In operation, the circuit of FIGURE 3 is normally in an initial state of rest. Upon the application of a trigger to terminal 70, 68 is lired to charge capacitor 78 and produce a current IP through the leads between w-w' and x-x with a gradually rising value having characteristics to be expected from a Series resonant circuit. The voltage Ec across 78 to ground is as shown in FIGUR-E 4. As Ec approaches the maximum charge of 78, two things happen. First, 68 is back-biased by diode 74 to cut-off and second, the firing voltage of 76 is exceeded such that it will re, discharging 78 and developing a current IA as shown. The current IA will have the characteristics indicated in FIG- URE 4 and will llow across terminals y-y. The period 1- of the current pulse indicated as Ip is determined by the relationship By appropriately selecting the values for L and C the amplitude and period of the currents can be suitably adjusted. The current wave form P shown in FIGURE 4 is quite satisfactory for performing the priming function required for MAD-R circuits. The current Wave form A in FIG- URE 4 is of a characteristic to satisfy the needs of advance current. The circuit of FIGURE 3 thus may be made to satisfy a number of distinct current requirements with prime type current only available from terminals w-w' advance characteristic current available only at terminals y-y and both advance and prime current available at terminals x-x. The circuit of FIGURE 3 thus may be utilized with any MAD-R circuit wherein a single phase of ad- Vance current is required.

For example, the magnetic cores of the stages I-N could be sampled destructively by having the x-x terminals thread the cores such that the pulse IP would prime the set cores and subsequently clear for readout.

The significance of FIGURE 3 to the cycle control operation above described is that the prime current permits an automatic delay between the triggering of the cores 1, 2, 3, n. This in turn permits the advantages above described including the use of a single commoned winding and an identical clock to effect the requisite sequenced sampling of a system such as 10.

While exemplary cores of a given geometry have been shown, it is contemplated that cores of other geometries may be utilized including the so-called composite core structures wherein individual bit positions are defined in an integral ferrite sheet.

Further, while the sampling drivers 50 have been indicated as part of the cycling control unit 30, it is frequently the case that the system such as 10 will demand and '7 include drivers 50 incorporated therein. In such event the cycle control may consist `simply of the cores 1-n with an appropriate circuit and connections plus some initiating7 device such as 34.

Changes in construction will occur to those skilled in the art and various apparently vdifferent modifications and embodiments may be made without departing fromv the scope ofthe invention. The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only. The actual scope of the invention is intended to be defined in the following claims when viewed in their proper` perspective against the prior art.

I claim:

1. An improved cycle control circuit for producing a cycle of sampling pulses to a series of stages of magnetic core devices comprising a plurality of control cores linked 4by a common winding in a common sense of clock ypulse developed MMF drive, a sampling pulse means connected to each control core to produce a pulse having a relatively long duration positive swing of relatively low amplitude followed by a relatively short duration swing of relatively high amplitude, the said sampling means for a given control core being connected to a succeeding control core and to a stage of magnetic core devices to apply said relatively high amplitude pulse to sample said stage device and set said succeeding control core, `and means to set one` of the said control cores to initiate sampling, wherein each of the said control cores .is a multi-aperture core having a major and at least a minor aperture and the samplingy pulse` References Cited UNITED STATES PATENTS 2,803,812 8/1957 Rajchman 340-l74 3,221,176 11/1965 Fritz 307-88 BERNARD KONICK, Primary Examiner.

TERRELL W. FEARS, Examiner.

R. MORGANSTERN, Assistant Examiner. 

1. AN IMPROVED CYCLE CONTROL CIRCUIT FOR PRODUCING A CYCLE OF SAMPLING PULSES TO A SERIES OF STAGES OF MAGNETIC CORE DEVICES COMPRISING A PLURALITY OF CONTROL CORES LINKED BY A COMMON WINDING IN A COMMON SENSE OF CLOCK PULSE DEVELOPED MMF DRIVE, A SAMPLING PULSE MEANS CONNECTED TO EACH CONTROL CORE TO PRODUCE A PULSE HAVING A RELATIVELY LONG DURATION POSITIVE SWING OF RELATIVELY LOW AMPLITUDE FOLLOWED BY A RELATIVELY SHORT DURATION SWING OF RELATIVELY HIGH AMPLITUDE, THE SAID SAMPLING MEANS FOR A GIVEN CONTROL CORE BEING CONNECTED TO A SUCCEEDING CONTROL CORE AND TO A STAGE OF MAGNETIC CORE DEVICES APPLY SAID RELATIVELY HIGH AMPLITUDE PULSE TO SAMPLE SAID STAGE DEVICE AND SET SAID SUCCEEDING CONTROL CORE, AND MEANS TO SET ONE OF THE SAID CONTROL CORES TO INITIATE SAMPLING, WHEREIN EACH OF THE SAID CONTROL CORES IS A MULTI-APERTURE CORE HAVING A MAJOR AND AT LEAST A MINOR APERTURE AND THE SAMPLING PULSE MEANS IS CONNECTED TO EACH CONTROL CORE BY A WINDING LINKING A CONTROL CORE MAJOR APERTURE AND THE SAMPLING MEANS CONNECTED TO A GIVEN CONTROL CORE IS CONNECTED TO A SUCCEEDING CONTROL CORE BY A WINDING LINKING THE CONTROL CORE THROUGH TURNS LINKING A MINOR AND MAJOR APERTURE THEREOF. 